Can We Have an Array of Custom Modules?

Verilog arrays of instances were added in Verilog-1995 (IEEE 1364-1995). They can be used with gates, user-defined primitives, and modules. Generates, which are more powerful but also more complex, were added in Verilog-2001.

Here is an example array of module instances:

DFF d[15:0] (clk, DFF_i, DFF_o);

For each port connection, if the size matches that of the formal parameter then it is connected to every instance. Otherwise each instance is connected to a part-select (or bit-select) of the expression.

it is not possible to do this directly (update: now after mark4o's answer I know that there is a way), but what you can do is using the generate statement to create multiple instances of your custom module and hook them up to your signals. Should look something like this:

wire DFF_i[15:0];
wire DFF_o[15:0];

generate
  genvar i;
  for (i=0; i<15; i=i+1) begin : dff
    custom i_custom(
       .clk(clk)
      ,.input(DFF_i[i])
      ,.output(DFF_o[i])
      );
  end
endgenerate

Otherwise there are probably some possibility during synthesis to use the correct custom modules, but I'm not an expert there.

Cheers, Daniel