Cross-Module Reference Resolution Error - Verilog Checks for Undefined Cross-Module Reference
I Am Working on an Environment Which Has Different Compilation Primitives as Like Comp_All_Modules - for Compiling All Modules Comp_Select_Modules - for...
I am working on an environment which has different compilation primitives as like
COMP_ALL_MODULES- for compiling all modulesCOMP_SELECT_MODULES- for compiling a selected set of modules
As such I am facing below error for COMP_SELECT_MODULES and not in COMP_ALL_MODULES
Error found while trying to resolve the cross-module reference. token 'BLK_B'
for below source code
assign clock = top.dut.BLK_B.clk;
It so happens that COMP_SELECT_MODULES does not compile BLK_B thus causing the error.
As in C programming, I tried 'ifdef checks as shown below. But that compiled out the clock assignment even for COMP_ALL_MODULES.
`ifdef top.dut.BLK_B
assign clock = top.dut.BLK_B.clk;
`else
assign clock = 1'b0;
`endif
Can you all please suggest about how to have a check for undefined Cross-module references as shown above?
1 Answer
Surely you want
`ifndef COMP_SELECT_MODULES
assign clock = top.dut.BLK_B.clk;
`else
assign clock = 1'b0;
`endif
The `ifdef statement tests whether a particular symbol has been defined (eg `COMP_ALL_MODULES or `COMP_SELECT_MODULES) NOT whether a particular place in the hierarchy exists or not.
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