Failure to Force a Signal with a Verified Path Using Uvm_Hdl_Force?
I'm Trying to Force a Signal to from Within a Uvm Sequence. I'm Using the Uvm_Hdl_Force Method. My Syntax, Run from Within the Task in My Uvm Sequence Is: If(!...
I'm trying to force a signal to from within a uvm sequence. I'm using the uvm_hdl_force method.
My syntax, run from within the task in my uvm sequence is:
if( !uvm_hdl_force ("ex_top.ent_lvl1.ent_lvl2.signalname",1'b1);
`uvm_fatal("CM_BUSY_SEQ","uvm_hdl_force failure of signalname")
I'm finding that this always failing.
I've verified the path and if I run uvm_hdl_check_path("ex_top.ent_lvl1.ent_lvl2.signalname") it returns 1, indicating that the path exists. Given that I'm not sure why the force is failing or what I else I should be checking?
I am also open to other methods of forcing the signal high if there are better methodologies then what I'm trying.
This is a mixed code design. The top level is verilog and the lower level level modules including the one where the specific signal I'm trying to force is located are VHDL.
Thank you
2 Answers
From provided snippet the solution is following, wrap the fatal to begin-end. As the ; will mean end of line and thus terminates the if clause. Or if you do not want to use begin-end do not put ; after the if clause.
// this ; invokes end of condition, to be safe wrap the fatal to begin end
// |
// V
if( !uvm_hdl_force ("tb_top.test",1'b1));
`uvm_fatal("CM_BUSY_SEQ","uvm_hdl_force failure of signalname")
// |
// |
// V
if( !uvm_hdl_force ("tb_top.test",1'b1)) begin
`uvm_fatal("CM_BUSY_SEQ","uvm_hdl_force failure of signalname")
end
// Or without ;
if( !uvm_hdl_force ("tb_top.test",1'b1))
`uvm_fatal("CM_BUSY_SEQ","uvm_hdl_force failure of signalname")
Moreover most tools support their own system-tasks for forcing values:
- Xcelium
$xm_force(string path,string value) - Questa
$signal_force(string path,string value)
There are possibly more parameters for these tasks, but I recommend to look for them inside the reference manual for your tool.
For the moment I have fixed this by moving away from uvm_hdl_force to a traditional force statement
Maya is a hardware enthusiast who tests and reviews smart home devices, smartphones, wearables, and audio gear. She focuses on practical consumer value and build quality.
