Is It Possible to Repeat a Gate in Structural Verilog?
I'm Going to Cascade Several Buffers in Verilog. My Sample Is as Below Which I've Define 16 Buffers Which Are Cascaded in Structural Definition: Bufx12...
I'm going to cascade several buffers in Verilog. My sample is as below which I've define 16 buffers which are cascaded in structural definition:
BUFX12 BUF01(dummy_wire[1],N62878);
BUFX12 BUF02(dummy_wire[2],dummy_wire[1]);
BUFX12 BUF03(dummy_wire[3],dummy_wire[2]);
BUFX12 BUF04(dummy_wire[4],dummy_wire[3]);
BUFX12 BUF05(dummy_wire[5],dummy_wire[4]);
BUFX12 BUF06(dummy_wire[6],dummy_wire[5]);
BUFX12 BUF07(dummy_wire[7],dummy_wire[6]);
BUFX12 BUF08(dummy_wire[8],dummy_wire[7]);
BUFX12 BUF09(dummy_wire[9],dummy_wire[8]);
BUFX12 BUF10(dummy_wire[10],dummy_wire[9]);
BUFX12 BUF11(dummy_wire[11],dummy_wire[10]);
BUFX12 BUF12(dummy_wire[12],dummy_wire[11]);
BUFX12 BUF13(dummy_wire[13],dummy_wire[12]);
BUFX12 BUF14(dummy_wire[14],dummy_wire[13]);
BUFX12 BUF15(dummy_wire[15],dummy_wire[14]);
Since I'm going to change number of buffers in my test design, I'm looking for a syntax such as for-loop to implement below structure in automated format but I don't know the correct structure for this. I want to know if is it possible and what is the correct syntax. Besides It would be better that implementation have names for instances.
2 Answers
Use an array of instances:
wire [15:1] other = {dummy_wire[14:1], N62878};
BUFX12 BUF [15:1] (dummy_wire, other);
You can use a generate loop if you wish, but the array of instances solution offered by @toolic is more compact:
assign dummy_wire[0] = N62878;
generate
genvar g;
for (g=1; g<16; g=g+1)
begin : in_Verilog_2001_you_need_this_and_it_needs_a_name
BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);
end
endgenerate
Verilog-2005 relaxed the rules regarding generate. This is legal in Verilog-2005:
assign dummy_wire[0] = N62878;
genvar g;
for (g=1; g<16; g=g+1)
BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);
And in SystemVerilog, you could tidy it up a little bit more:
assign dummy_wire[0] = N62878;
for (genvar g=1; g<16; g++)
BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);
But personally, I like the Verilog-2001 version: it's more explicit.
MCVE:
module M;
wire [15:0] dummy_wire;
wire N62878;
assign dummy_wire[0] = N62878;
generate
genvar g;
for (g=1; g<16; g=g+1)
begin : in_Verilog_2001_you_need_this_and_it_needs_a_name
BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);
end
endgenerate
endmodule
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