Is There a Specific Way to Stop the Test/Simulation in Case Condition Failure?
I Want the Test to Stop in the Case of a Failure Condition. I Used Uvm_Error, but This Only Produces a Text Message. Is There a Specific Way to Stop the...
I want the test to stop in the case of a failure condition.
I used UVM_ERROR, but this only produces a text message.
Is there a specific way to stop the test/simulation in case condition failure in addition to the text message (something like assert in systemVerilog)?
1 Answer
Add the +UVM_MAX_QUIT_COUNT=1 runtime option on your simulator command line. This will end the simulation after the 1st UVM_ERROR.
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