Uvm_Event and System Verilog Event Difference
What Is the Advantage of Uvm_Event over the Systemverilog Event? Can Someone Explain with Small Pseudo Code? 2 Answers Uvm Is Nothing but a Wrapper Library...
What is the advantage of uvm_event over the SystemVerilog event ?
Can someone explain with small pseudo code ?
2 Answers
UVM is nothing but a wrapper library developed over SystemVerilog. So, the uvm_event and SystemVerilog events are the same but uvm_event has some additional functionality.
From the UVM Class reference:
The uvm_event class is a wrapper class around the SystemVerilog event construct. It provides some additional services such as setting callbacks and maintaining the number of waiters.
A traditional Systemverilog event does not have functionality to pass data when event is triggered. While uvm_event adds this functionality. So, you can pass the transaction class handle when some event is triggered.
Just like traditional SV events, uvm_event also has trigger and persistent trigger modes (while SV has wait(ev.triggered) and @(ev) counterparts).
You can also add callbacks whenever an event is triggered. This is done by registering a callback class with particular event.
As far as events are concerned, they seem to be costly in terms of overhead. You can get many examples on uvm_event like this one.
There are no advantages of using uvm_event over what is in the basic SystemVerilog event construct unless you need the extra functionality provided by the uvm_event The additional features include adding a uvm_object to be associated with the trigger, and booking information like keeping track of the number of waiters and the last time the uvm_event was triggered.
I have not seen much use for these additional features, and events in general are usually too low level for most testbenches to be dealing with.
Marcus Vance is a cybersecurity auditor and technology writer dedicated to educating the public about online safety, data privacy regulations, enterprise security, and emerging cyber threats.
